1. Field of the Invention
Generally, the present disclosure relates to the field of semiconductor manufacturing, and, more particularly, to contact areas of transistors having a shallow drain and source dopant profile.
2. Description of the Related Art
Semiconductor devices, such as advanced integrated circuits, typically contain a large number of circuit elements, such as transistors, capacitors and the like, which are formed on an appropriate substrate having formed thereon a crystalline semiconductor layer. Due to the large number of circuit elements and the required complex layout of modern integrated circuits, the electrical connections of the individual circuit elements may generally not be established within the same level on which the circuit elements are manufactured, but require one or more additional “wiring” layers, which are also referred to as metallization layers. These metallization layers generally include metal-containing lines, providing the inner-level electrical connection, and also include a plurality of inter-level connections, which are also referred to as “vias,” that are filled with an appropriate metal and provide the electrical connection between two neighboring stacked metallization layers.
To establish the connection of the circuit elements to the first metallization layer, an appropriate contact structure is provided that connects to a respective contact region of a circuit element, such as a gate electrode and the drain/source regions of field effect transistors, and to a respective metal line in the first metallization layer. The vertical contact structure, including a plurality of contacts or contact plugs, is formed in an inter-layer dielectric material that encloses and passivates the circuit elements.
The continuing shrinkage of dimensions of circuit elements, such as transistors, has been, and will remain, a major goal of semiconductor manufacturers, since significant gain in performance of semiconductor devices may be accomplished in terms of operating speed, production costs and the like. For example, the gate length of field effect transistors has now reached 0.05 μm and less and, hence, fast and powerful logic circuitry, such as microprocessors, storage devices and the like, may be formed on the basis of these transistors, due to increased packing density, thereby also providing the possibility of incorporating more and more functions into a single die region. For instance, the amount of storage incorporated into modern CPUs has steadily increased, thereby enhancing overall performance of microprocessors. In other cases, complex analog and digital circuitry may be provided on the same semiconductor chip, thereby offering enhanced control functionality for a plurality of electronic devices. Upon reducing the feature sizes of the semiconductor circuit elements in the device level, however, the dimensions of the metal lines and vias in the wiring level of the semiconductor devices also have to be reduced since the contact areas of the circuit elements have to be connected to the metallization level so that at least the contact structure and lower lying metallization levels may also require a significant reduction in size of the individual metal lines and vias.
It should be appreciated that, for highly scaled semiconductor devices, typically, electrical performance of the metallization system including the contact level has a significant influence on the overall performance of the semiconductor device due to parasitic capacitance and the parasitic resistivity of the metal features. Consequently, in modern semiconductor devices, frequently, highly conductive metals, such as copper and the like, may be used in combination with dielectric materials of reduced permittivity in order to restrict signal propagation delay caused by the metallization system. On the other hand, in the device level, a reduction of the channel length of field effect transistors in combination with very high dopant concentrations in the drain and source regions and gate electrodes may be used in view of reducing the overall series resistance of the individual circuit elements. However, in order to further reduce the series resistance of transistor devices and other circuit elements in the device level, the resistivity of highly doped silicon-based semiconductor areas is typically reduced by incorporating an appropriate metal species, for instance in the form of a metal silicide. The corresponding metal silicide may have a reduced sheet resistivity compared to even highly doped semiconductor materials and, hence, a respective manufacturing sequence is typically incorporated in sophisticated process techniques in order to form appropriate metal silicide regions in the drain and source areas or other contact areas of circuit elements, possibly in combination with providing a respective metal silicide in the gate electrodes.
Recently, well-approved metal silicides in the form of cobalt di-silicide are increasingly being replaced by metal silicide components of enhanced conductivity, such as nickel silicide. Although significant performance advantages may be associated with the incorporation of a nickel silicide into the drain and source areas of the transistors, it turns out, however, that, in the manufacturing sequence for forming metal silicides, significant yield loss and a less than expected increase of performance may be observed in view of device failures, which may frequently be caused by short circuits “shorting” the PN junctions of the transistors in the drain and source areas.
These device failures are frequently associated with a pronounced surface topography of the active semiconductor regions, which in turn may be caused by a complex manufacturing sequence for forming sophisticated transistor devices, in particular with P-channel transistors. For example, a significant gain in performance may be accomplished by inducing certain strain conditions in the active regions of the transistors since a strained silicon material may have significantly altered electronic characteristics, in particular with respect to charge carrier mobility, which may be taken advantage of with respect to increasing overall conductivity and thus switching speed of the transistors. To this end, appropriate semiconductor alloys, such as silicon/germanium and the like, are frequently incorporated into a portion of the active regions by selective epitaxial growth techniques in order to obtain a strained state of the grown semiconductor alloy due to a mismatch of the natural lattice constants of these materials with respect to the lattice constant of the silicon base material.
In other sophisticated approaches, the electronic characteristics of at least a portion of the active region may be adjusted, for instance, in terms of threshold voltage of the transistors by incorporating an appropriate semiconductor alloy, such as a silicon/germanium alloy, which may thus result in a modification of the band gap energy at the vicinity of an interface formed by a gate dielectric material and the active region. For example, in sophisticated approaches, gate electrode structures of field effect transistors may be provided on the basis of a high-k dielectric material in combination with a metal-containing electrode material, which may require appropriate adaptations of the electronic characteristics of the active region, at least in the vicinity of the gate dielectric material for at least some transistor devices. Also in this case, sophisticated selective epitaxial growth techniques are usually applied, which may also result in a modified surface topography, thereby causing significant irregularities upon forming the metal silicide regions, in particular of P-channel transistors, as will also be explained in more detail with reference to FIGS. 1a-1f. 
FIG. 1a schematically illustrates a top view of a semiconductor device 100 in which a transistor 150, i.e., a field effect transistor, is provided, in the form of a P-channel transistor. As illustrated, the transistor 150 comprises a semiconductor region 103, which is also referred to herein as an active region, indicating that at least one transistor is to be formed in and above the corresponding semiconductor region. The active region 103 is typically formed from a silicon-based semiconductor layer, which is appropriately laterally divided into a plurality of active regions by means of an isolation region 102, such as a shallow trench isolation region comprised of silicon dioxide, silicon nitride and the like. Furthermore, a gate electrode structure 160 is formed on the active region 103 and extends also into the isolation region 102 as may be required for connecting to other transistors and/or for allowing the reliable contacting of the gate electrode structure 160 by appropriate contact elements, as is also discussed above. As indicated above, the isolation region 102 may laterally delineate the active region 103, thereby defining respective sidewalls 103S, which thus represent the boundaries of the active region 103 in a width direction, indicated as W. Similarly, in a length direction L, sidewalls 103T represent the boundaries of the active region 103, which, in the illustrative embodiment, may have a substantially rectangular shape.
FIG. 1b schematically illustrates a cross-sectional view taken along the line Ib of FIG. 1a. As illustrated, the isolation region 102 formed in a semiconductor layer 103H may be significantly recessed, as indicated by 102R, with respect to the active region 103. The degree of recessing 102R may significantly depend on the process history of the transistor 150, wherein, in sophisticated applications, the corresponding sidewalls 103T may be represented by rather steep sidewalls, which may have a significant influence on the finally obtained dopant profile of drain and source regions 151. Moreover, in the manufacturing stage shown, the gate electrode structure 160 is formed on the active region 103 and comprises a sidewall spacer structure 165, which is typically used as an implantation mask when adjusting the concentration profile of the drain and source regions 151 and which may also be used in the subsequent processing, at least partially, as a mask for forming metal silicide regions in the active region 103. Furthermore, the gate electrode structure 160 comprises an electrode material 161, such as a polysilicon material and the like, possibly in combination with a metal-containing electrode material 162, such as titanium nitride and the like. Furthermore, a gate dielectric layer 164, possibly in combination with a high-k dielectric material 163, may be provided in sophisticated applications. Furthermore, as shown, a strain-inducing semiconductor alloy 103A, for instance in the form of a silicon/germanium alloy and the like, may be provided so as to induce certain strain conditions in order to improve overall transistor performance. For example, by incorporating a silicon/germanium alloy as the material 103A, a compressive strain is induced, which in turn may result in superior conductivity of holes, thereby improving performance of P-channel transistors. Furthermore, a semiconductor alloy 103B, such as a silicon/germanium alloy, may be provided as a part of the active region 103 in order to adjust the threshold voltage of the transistor 150 in combination with the gate electrode structure 160, which may have incorporated therein a high-k dielectric material and the electrode material 162.
It should be appreciated that, in some sophisticated transistor architectures, a buried insulating layer (not shown) may be formed below the semiconductor layer 103H, when a silicon-on-insulator (SOI) configuration is to be used. In this case, the significant recessing 102R may extend almost down to the buried insulating layer.
FIG. 1c schematically illustrates a cross-sectional view of the device 100 along the line Ic of FIG. 1a. As shown, also in this case, the sidewalls 103S, i.e., the sidewalls delineating the active region 103 in the length direction (see FIG. 1a), may have a rather steep configuration. Moreover, as shown, the drain and source regions 151 may extend to a certain depth within the active region 103, depending on the implantation parameters used for incorporating the drain and source dopant species, as will be described later on in more detail. Furthermore, in an SOI architecture, the depth of the drain and source regions may be selected so as to extend to the buried insulating layer, wherein, typically, the dopant concentration at the bottom of the deep drain and source regions 151D is less than in an upper portion thereof.
It should be appreciated that, for convenience, the gate electrode structure 160, which would actually not be visible in this section, is indicated in dashed lines.
The semiconductor device 100 as shown in FIGS. 1a-1c may be formed on the basis of the following process strategies. The size, position and shape of the active region 103 is determined by forming the isolation region 102, which may be accomplished by applying well-established lithography, etch, deposition, planarization and anneal techniques in which appropriate trenches are formed in the semiconductor layer 103H, thereby obtaining a plurality of active regions such as the region 103. Prior to or after forming the isolation region 102, the basic dopant concentration in the various active regions 103 may be established by, for instance, ion implantation in combination with an appropriate masking regime so as to provide the active regions for P-channel transistors and N-channel transistors, possibly with different threshold voltage values, as required by the overall design rules. Thereafter, appropriate materials are deposited or formed and are appropriately patterned on the basis of highly complex lithography techniques and etch processes in order to form the gate electrode materials 161, 162 and the dielectric materials 163, 164. A corresponding process sequence may comprise a plurality of complex patterning processes in order to incorporate appropriate work function metal species for the corresponding transistor type under consideration.
Furthermore, as discussed above, if the semiconductor alloy 103B is to be provided, for instance when requiring a corresponding adaptation of the electronic characteristics, for instance when providing sophisticated gate materials, the complex gate patterning process is preceded by a process sequence in which an appropriate semiconductor alloy is selectively grown on those active regions that require a corresponding adaptation of the electronic characteristics. During the corresponding process sequence, hard mask materials have to be provided and patterned, followed by cleaning processes and the selective epitaxial growth process, wherein this sequence may generally result in a more or less pronounced material loss in the isolation regions 102, for instance caused by patterning the hard mask materials, performing cleaning processes and removing the hard mask materials. After patterning the gate electrode materials 161, 162, the processing may be continued by forming cavities in the active region 103 in order to incorporate the semiconductor material 103A, if required, wherein also a complex process sequence is to be applied, i.e., the etching of the active region 103, while masking any other active regions that do not require the incorporation of the strain-inducing semiconductor material, such as active regions of N-channel transistors. Furthermore, the complex process may include performing any cleaning processes and finally depositing the material 103A, followed by the removal of any hard mask materials, which may also result in significant material erosion in the isolation regions 102. Thereafter, if required, implantation processes are typically applied for forming a portion of the drain and source regions 151.
Generally, it is to be noted that, upon reducing the overall transistor dimensions and in particular the gate length, i.e., in FIG. 1b, the horizontal extension of the electrode materials 161, 162, an appropriate adaptation of the drain and source concentration profiles has to be applied in order to preserve the desired transistor characteristics, such as channel controllability, leakage currents and the like. On the other hand, in view of reducing the overall series resistance in the transistors, a relatively high dopant concentration is to be provided in the drain and source regions 151. Frequently, in the vicinity of a channel area 155, the depth of the concentration profile is to be selected less compared to the depth of the concentration profile of “deep” drain and source regions 151D. To this end, typically any drain and source extension regions 151E may be formed, for instance by providing an appropriate offset spacer element (not shown) and incorporating drain and source dopant species with an appropriate implantation energy and dose. Thereafter, the spacer structure 165 may be formed and further implantation processes are typically applied so as to incorporate further drain and source dopant species in order to form the regions 151D that appropriately connect to the extension regions 151E. Similarly, the depth of the concentration profile of the regions 151D is to be reduced upon further shrinking the overall transistor dimensions. Thus, the depth of the areas 151D may be comparable or even less than the degree of recessing 102R.
FIG. 1d schematically illustrates the device 100 in a further advanced manufacturing stage. As shown, a metal silicide 166 is formed in the gate electrode structure 160 and also a metal silicide 156 is formed in the active region 103. As discussed above, typically, the metal silicide regions 156 are provided so as to reduce the overall contact resistivity between contact elements (not shown) to be formed in a later manufacturing stage, which in turn connect the transistor 150 to a metallization system still to be formed. In highly scaled semiconductor devices, the contribution of the contact resistivity with respect to the overall performance of the transistor 150 is increasingly gaining in importance so that sophisticated materials are typically provided in the active region 103 in view of superior device performance. For example, nickel, possibly in combination with a certain amount of platinum, is frequently used in order to form nickel silicide. It turns out, however, that nickel silicide forms a Schottky barrier with a semiconductor material, wherein the height of the barrier may be significantly reduced when increasing the dopant concentration of the adjacent semiconductor material. Thus, in view of providing a maximum surface area of the metal silicide 156 that is available for charge carrier exchange with the drain and source regions 151, any interfaces formed by the silicide material 156 and semiconductor material should be positioned within highly doped areas of the drain and source regions 151. If a relatively high Schottky barrier exists between a moderately doped semiconductor material and the nickel silicide 156, extension of the metal silicide 156 into the remaining active region 103, i.e., “shorting” the corresponding PN junctions, may be disadvantageous in bulk configuration due to significantly increased leakage currents and other parasitic effects, since even a short circuit may be induced for operating voltages that are comparable to the relatively high Schottky barrier. Furthermore, a “shorting” of the PN junctions, although tolerable, may also be disadvantages in an SOI architecture, since the relatively high Schottky barrier caused by the moderate doping concentration in the well region may result in increased series resistance of the transistor, even though the transistor may remain substantially functional. On the other hand, the reduced dopant concentration in the deeper areas of the drain and source regions 151 may also cause reduced transistor performance, even though the metal silicide regions 156 may be embedded in the drain and source regions, since current flow from contact elements to the transistor may preferably occur via the metal silicide. In this case, however, the deep areas of the metal silicide 156 may contribute to a significantly increased overall resistance due to the relatively pronounced Schottky barrier.
That is, during the silicidation process, typically an appropriate refractory metal is deposited and is subsequently heat treated so as to initiate silicon and metal diffusion. On the other hand, chemical reaction is substantially suppressed on any dielectric surface areas. Consequently, the spacer structure 165 and the isolation region 102 may act as efficient silicidation masks, while on the other hand the sidewalls 103T and 103S (see FIG. 1c) are efficiently silicided, thereby forming the metal silicide 156 that may thus be positioned outside of the deep drain and source areas 151D or may be positioned in an area of the drain and source regions which have a reduced dopant concentration, thereby encountering an increased Schottky barrier.
FIG. 1e schematically illustrates the situation in the cross-sectional view as indicated in FIG. 1a as section Ic, wherein also at the sidewalls 103S, metal silicide 156D extends deeply into the active region 103.
FIG. 1f schematically illustrates a top view of the device 100 in which the peripheral areas 103P at or in the vicinity of the sidewalls 103T, 103S are illustrated, in which the metal silicide may extend deeply into the active region 103, thereby possibly causing significant device failures or generally reducing overall performance of the transistor devices.
Consequently, in particular, sophisticated P-channel transistors may suffer from increased yield loss and reduced performance, when the gate length may be 40 nm and less in transistor architectures requiring the incorporation of a strain-inducing silicon/germanium alloy, thereby making this basically a very promising approach less attractive in volume production environments. Therefore a plurality of approaches has been discussed. For example, avoiding the significant recessing of the isolation structures 102 during the formation of sophisticated P-channel transistors has been proposed, however, without giving any details as to the practical implementation of an improved strategy in this respect. Another alternative would be the increase of the drain and source dopant concentration by implanting a higher dopant dose. As discussed above, however, significantly modifying the dopant concentration in highly scaled transistors may be associated with a plurality of additional effects, which in turn may not be compatible with the overall device requirements. In this respect, it turns out that the dopant concentration is strictly limited for a technology of 40 nm and less, since otherwise the drain and source regions would unduly penetrate the channel region and increase the device leakage currents. That is, a higher dose implantation process without additional lateral dopant diffusion into the channel region would require increased width of the corresponding spacer elements, which is generally not compatible with sophisticated device architectures due to a limited pitch of gate electrode structures in densely packed device regions. Therefore, an increase of implantation dose may not be a promising solution.
Instead of increasing the implantation dose, the implantation energy could be increased in order to generate a more homogeneous dopant profile throughout the depth of the drain and source regions. It turns out, however, that significant increase of the implantation energy may not be compatible with the overall gate configuration, that is, undue dopant incorporation into the channel region may occur upon increasing the implantation energy.
A promising approach is described in the non-published U.S. patent application Ser. No. 13/052,583, filed by the applicant of the present application, entitled “Shallow Source and Drain Architecture in an Active Region of a Semiconductor Device Having a Pronounced Surface Topography by Tilted Implantation.” According to this concept, tilted implantation processes may be applied with tilt angles of 30 degrees or greater in an attempt to incorporate additional dopant species into the deeper drain and source areas through exposed sidewall surface areas in order to embed the resulting deep metal silicide regions in a semiconductor material of increased dopant concentration. Upon applying this concept, however, it has been observed that the resulting gain in transistor performance is less pronounced as expected, thereby indicating that the significant surface topography of the active region of, in particular, P-channel transistors still significantly influences the behavior of sophisticated semiconductor devices. Therefore, the concept disclosed in this patent application may still require additional improvement in order to provide a strategy appropriate for volume production techniques in view of semiconductor devices including p-channel transistors having a gate length of 40 nm and less in combination with sophisticated gate electrode structures.
In view of the situation described above, the present disclosure relates to manufacturing techniques and semiconductor devices in which appropriate contact areas, such as metal silicide regions, may be provided in active regions requiring a sophisticated dopant profile and having a pronounced surface topography, while avoiding or at least reducing the effects of one or more of the problems identified above.